[LLVMdev] how to detect data hazard in pre-RA-sched

[Andrew Trick]

On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:

> hi, LLVM, 
> 
> I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to optimize processor pipeline? 

The hazard recognizer enforces the instruction itineraries that are defined for some subtargets. The itineraries specify resource usage at each pipeline stage and latency. The "hazards" being recognized are resource conflicts, like two independent instructions using the FP unit, or read after write latency. It does not deal with WAR physical register hazards.

(Targets are migrating to a more flexible and efficient machine model now that does not use the hazard recognizer.)

-Andy