[LLVMdev] how to detect data hazard in pre-RA-sched
navy.xliu at gmail.com
Tue Sep 24 19:59:35 PDT 2013
Thank you for answering my question.
What's the status of misched? is it experimental? I found it is disabled by
default for all architectures(3.4svn). I also don't understand the
algorithm. Could you point to me more papers or text materials about your
approach? it seems that you want to balance register pressure and ILP in
On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
> > hi, LLVM,
> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp.
> I still don't understand how llvm detects data hazard in pre-RA-sched.
> pre-RA-sched is based on SDNode and all operands are vregs. Even you can
> calculate the operators of SDNodes, the data hazard in vreg are not same as
> physical register data hazard. Is it useful to optimize processor pipeline?
> The hazard recognizer enforces the instruction itineraries that are
> defined for some subtargets. The itineraries specify resource usage at each
> pipeline stage and latency. The "hazards" being recognized are resource
> conflicts, like two independent instructions using the FP unit, or read
> after write latency. It does not deal with WAR physical register hazards.
> (Targets are migrating to a more flexible and efficient machine model now
> that does not use the hazard recognizer.)
> I don't understand this statement. what's the meaning of "more flexible &
efficient machine model". I know intel x86 processors are featured with
aggressive out of order function, but arm and mips don't have it. Server
processor can have, embedded processor will not. Compiler writers still
need to consider instruction pipeline and multiple issue.
Our processor still uses mips-like multiple-stage pipeline, almost same as
what textbook taught me. We suffer from pipeline stalls and manager to
improve issue rate using instruction scheduling. by now, I use
post-RA-sched because It can build graph whose edges are dependencies. the
dependencies are real basing on physical register and instruction
attributes. Because misched happens before register allocation, I don't
think I can make use of it to resolve data hazard. am I right?
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