[LLVMdev] how to detect data hazard in pre-RA-sched
navy.xliu at gmail.com
Sat Sep 21 20:02:07 PDT 2013
I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I
still don't understand how llvm detects data hazard in pre-RA-sched.
pre-RA-sched is based on SDNode and all operands are vregs. Even you can
calculate the operators of SDNodes, the data hazard in vreg are not same as
physical register data hazard. Is it useful to optimize processor pipeline?
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