[LLVMdev] 64 bit special purpose registers

Pranav Bhandarkar pranavb at codeaurora.org
Mon Sep 10 07:59:33 PDT 2012

> Normally there is a 64 bit register that is the result of certain multiply
and divide instructions.
>It's really 2 32 bit registers.
>This is like  HI[0]/Lo[0]
>In fact there are four such pairs, only the 0th pair available to basic
multiply and divide.
>But DSP instructions have access to 4 , Hi[i],Lo[i], i=0..3
>We want the register allocator to allocate them for us but also we need to
have them paired,
>i.e. Hi[1],Lo[1]

>So in principle if you have a 64 bit register you can have two 32 bit
registers inside.

Look at the Hexagon backend which also has 64 bit register pairs and only
successive even-odd 32 bit registers can be paired together.

>If you tell the register allocator that you have 64 bit registers, then it
wants to assume that 64 bit
>is a legal operand type and then llvm assumes that you have native
instructions for all the 64 bit
>types, and we don't have that in mips32, for example. So you would have to
lower them all yourself.


Even in Hexagon, not all operations are legal on i64. So, like Michael said,
you should "setOperationAction" for those operations (and i64) to "Expand".

However, I am guessing, in your case, you have more operations that are
illegal than ones that are legal for i64 types ?



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