[LLVMdev] Multiple-Pipeline Itinerary

Anton Korobeynikov anton at korobeynikov.info
Fri Oct 7 09:31:20 PDT 2011

Hi Hal,

> //  InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
> //                               InstrStage<1, [A9_AGU]>],
> //                              [3, 1], [A9_LdBypass]>,
> If there is an operand dependency, does the scheduler assume that the
> instruction is held in A9_Pipe1 or in A9_AGU until the operand is ready?
Yes. Watch these [3, 1] numbers. Basically it's the number of cycles
until the result ir ready (for output operands) or cycle # when the
operand is read (for input operands)

With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

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