[LLVMdev] Multiple-Pipeline Itinerary

[Hal Finkel]

In the example provided:

//  InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
//                               InstrStage<1, [A9_AGU]>],
//                              [3, 1], [A9_LdBypass]>,

If there is an operand dependency, does the scheduler assume that the
instruction is held in A9_Pipe1 or in A9_AGU until the operand is ready?

Thanks again,
Hal

On Fri, 2011-10-07 at 00:44 +0400, Anton Korobeynikov wrote:
> Hal,
> 
> > What is the difference between Reserved and Required?
> Think about them like read/write locks.
> 
> E.g. if FU is Reserved (=read lock) is can be Reserved multiple times,
> but never Required.
> If FU is Required (=write lock) it cannot be neither Reserved nor Required.
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory