[LLVMdev] Advice on architecture research project?

[Pekka Jääskeläinen]

Hi Benjamin,

On 06/10/2011 09:31 PM, Benjamin Ylvisaker wrote:
> The angle I'd like to explore is combining a queue-based ISA with a
> more conventional micro-architecture.  To the first order, all you
> have to do in the micro-architecture is replace the architectural
> register to physical register renaming with a queue position to
> physical register "renaming".  My (totally unsupported for now) belief
> is that a queue-based ISA would make it easier/more efficient to
> implement some recent micro-architectural research ideas for scalable
> cores, like banked register files.

You might be worth it to give our TCE project [1] and the TTA architecture
it uses as the processor template a look. Seems there's some similarity
in goals here. Split reg files are the norm in the TTA cores designed
with TCE.

Also the TCE toolset might provide you an easy platform to experiment with
special instructions you might have in mind. Those FIFO access operations, for
example, are trivial to implement in TCE and we have already had some designs
with such FIFO instructions in the past.

TCE generates compiler backends for the designed TTAs automatically using LLVM.
The (instruction) cycle accurate processor simulator adapts to the new
designs on the fly.

[1] http://tce.cs.tut.fi

BR,
-- 
--Pekka Jääskeläinen