[LLVMdev] Advice on architecture research project?

[ankur deshwal]

> I am interested in working on a little architecture project that
> involves modifying an ISA in some non-trivial ways and seeing what
> impact it has on instruction frequencies (and other such metrics).
> Clearly I'll need to hack on a compiler backend, and I thought that
> LLVM might be a good choice since among mature compiler
> infrastructures it's fairly young and presumably relatively clean.

You are at the right place. Its very clean as compared GCC and
Open64 for sure. I am quite new to LLVM but can already see the
clarity due to modular design.

>  I
> will also need to choose an ISA and a functional simulator (which I
> will also need to hack) for the evaluation.  I'm not particularly
> interested in micro-architecture level accuracy, so I'd rather avoid
> that complexity if possible.  I think I'd rather start with an ISA
> more in the RISC family.
> Does anyone have a suggestion about ISAs for which there is a good
> LLVM backend and an open source/customizable functional simulator?

I agree that ARM is a good choice.  MIPS is less well supported in LLVM,
I think.
But don't count out venerable X86.  There are simulators available for
it, both open- and closed-source.

I have a similar problem. I need the performance based study so only options
seem to be "cycle-accurate" simulator or the real hardware. Due to the poor
performance of cycle-accurate simulators in terms of accuracy, I am not
considering currently.
Among the real hardware, X86 is a favorable choice due to wide
availability for me
to experiment with different configurations. However, its CISCity
scares me too.
Is it possible to choose a small subset of X86 ISA, without scary addressing
modes and emitting only those instructions from LLVM. Will generally available
hardware profiling tools work fine in such a case. Is there any info
available for
any such subset has been defined and used by someone already?


Note that things like instruction frequencies are highly ISA-dependent.
If possible, it is best to evaluate your ideas on more than one target,
just to see what the effects are.  What other sorts of things do you
want to study?
If, long-term, you are planning to do serious studies of performance
impacts, I very highly recommend you not rely on simulators if at all
possible.  I have never met a simulator ("cycle-accurate" or not) that
even comes close to giving reasonable performance predictions.
I admit this is rather difficult to do if you are exposing some new
hardware magic to the ISA.  In cases like this I have long believed that
availability of compiler and simulator source code should be a bare
minimum prerequisite for publication.  Unfortunately, I seem to be in a
rather small minority.
                            -Dave
My worries about the same comes from some studies like [1]

[1] http://www.csl.cornell.edu/~vince/papers/wddd08/wddd08_sim.pdf

Enjoy,
Ankur