[LLVMdev] Advice on architecture research project?

Benjamin Ylvisaker benjaminy at alumni.cmu.edu
Fri Jun 10 11:31:25 PDT 2011

On Jun 9, 2011, at 8:09 PM, David A. Greene wrote:

> Note that things like instruction frequencies are highly ISA- 
> dependent.  If possible, it is best to evaluate your ideas on more  
> than one target, just to see what the effects are.  What other sorts  
> of things do you want to study?
> If, long-term, you are planning to do serious studies of performance  
> impacts, I very highly recommend you not rely on simulators if at  
> all possible.  I have never met a simulator ("cycle-accurate" or  
> not) that even comes close to giving reasonable performance  
> predictions.
> I admit this is rather difficult to do if you are exposing some new  
> hardware magic to the ISA.  In cases like this I have long believed  
> that availability of compiler and simulator source code should be a  
> bare minimum prerequisite for publication.  Unfortunately, I seem to  
> be in a rather small minority.

The idea I am interested in investigating is operand queue-based (as  
opposed to register file-based) ISAs.  As far as I know, there is one  
group that has done a significant amount of work on this idea, the  
SOWA lab at The University of Electro-Communications in Tokyo.  They  
put forward new and interesting micro-architectural ideas along with  
the new ISA ideas, which I think has limited the impact of their work,  
because doing a credible design and evaluation of entirely new micro- 
architectures is so hard.  See, e.g.:

http://bit.ly/iStSmS [ACM Digital Library]

The angle I'd like to explore is combining a queue-based ISA with a  
more conventional micro-architecture.  To the first order, all you  
have to do in the micro-architecture is replace the architectural  
register to physical register renaming with a queue position to  
physical register "renaming".  My (totally unsupported for now) belief  
is that a queue-based ISA would make it easier/more efficient to  
implement some recent micro-architectural research ideas for scalable  
cores, like banked register files.

Doing a full-blown micro-architecture exploration and evaluation is  
way beyond what I have time for, but before I get there I need to  
address some ISA-level issues.  Naive queue-based ISAs lead to very  
inefficient code, because you need lots of extra instructions for  
shuffling data around the queue to get values in the right order.   
(2x-5x more instructions executed is not uncommon.)  So what I'm  
hoping to do is explore some ISA tweaks and verify that it's possible  
to bring down the number of queue overhead instructions to a  
manageable percentage.

Does anyone have any experience with or advice about particular  
simulators/emulators?  What I'm most interested in is easy  
modifiability.  QEMU looks like an interesting option.


More information about the llvm-dev mailing list