[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
anton at korobeynikov.info
Thu Apr 14 08:04:00 PDT 2011
> My instruction itineraries are defined to all take 1 machine cycle to
> complete (my target is fully pipelined) but with values 2 and 3
> specifying when the result is ready (not all instructions have
> forwarded results) and 2 as parameter for when the operands are read.
Does this mean that your instruction always have single cycle delay
slot? The latency right now is definitely negative, since you
specified that the instruction takes single cycle, but operands are
read on the second cycle.
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
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