[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
mangepe at gmail.com
Thu Apr 14 04:03:44 PDT 2011
While trying to create back end in LLVM I have stumbled upon a problem
I have trouble to get past, hopefully someone can give me hints on
what I am doing wrong. The problem is that the assertion in the file
ScheduleDAGList.cpp row 187 is triggered: "Negative latency". How does
My target has one issue unit, therefore my Schedule.td file only
contain one functional unit.
My instruction itineraries are defined to all take 1 machine cycle to
complete (my target is fully pipelined) but with values 2 and 3
specifying when the result is ready (not all instructions have
forwarded results) and 2 as parameter for when the operands are read.
mvh (kind regards)
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