[LLVMdev] Paired register allocation problem

[Charles Davis]

Artur Pietrek wrote:
> I'd appreciate if someone could enlighten me on pseudo instructions.
> These work fine if I want to print assembly. What if I want to generate
> a binary file directly: how can I expand something like this:
> mov $p0, $p1
> into two instructions:
> mov $r0, $r2
> mov $r1, $r3
> 
> Another problem: All of my instructions which operates on 64bit
> operands, take pairs of 32bit registers. However in some of these
> instructions registers are encoded as a pair number and in some as two
> single register numbers for each pair.
> 
> Similar problem with immediates which not fit in 10bits - they are
> encoded as separate upper22 bits and lower10 bits (64 bits long version
> of instruction instead of 32 bits).
I can't help you directly, but I can point you in the right direction.

Take a look at the 'MC' library. This is the library that's responsible
for generating native binary code. (It's not finished yet, by the way.)
If you want this kind of support from LLVM, you'll have to hook your
backend into MC.

Chip