[LLVMdev] Paired register allocation problem
anton at korobeynikov.info
Mon Feb 22 09:10:19 PST 2010
> I've compared again everything to systemz. The problem was I've defined
> paired class as a subclass of Register class instead of RegisterWithSubRegs
> class. After change the code is OK.
> Yes, I have those.
> If you don't mind I'll ask few compilers/LLVM newbie questions.
> I'd appreciate if someone could enlighten me on pseudo instructions.
> These work fine if I want to print assembly. What if I want to generate a
> binary file directly: how can I expand something like this:
> mov $p0, $p1
> into two instructions:
> mov $r0, $r2
> mov $r1, $r3
Well, just have a post-RA pass, which expands these
pseudo-instructions into real ones? Look how things are performed on
This is general goodness for post-RA scheduler as well.
> Another problem: All of my instructions which operates on 64bit operands,
> take pairs of 32bit registers. However in some of these instructions
> registers are encoded as a pair number and in some as two single register
> numbers for each pair.
> Similar problem with immediates which not fit in 10bits - they are encoded
> as separate upper22 bits and lower10 bits (64 bits long version of
> instruction instead of 32 bits).
So, what's the problem here? All such weirdness should be handled
inside code emitter....
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
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