[LLVMdev] Paired register allocation problem
anton at korobeynikov.info
Mon Feb 22 09:12:58 PST 2010
> I was wondering if this would be more practical in LLVM (of which I am
> ignorant but curious) or whether the illusion of a single 64-bit
> register also persists there until it is too late.
It makes sense to have such pseudo-instructions up to RA - this
simplifies many things alot. However, one can do a post-RA Machine
Instruction pass and split such pseudo-instructions into "normal"
ones. post-RA scheduler will be happy to schedule the single
instructions to ensure necessary latencies.
This is already done for movt/movw pairs on ARM.
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
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