[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
Micah.Villmow at amd.com
Thu Dec 10 15:09:40 PST 2009
I don't see how this helps with the splitting of the Other node as it isn't the Dest that is the problem, but the second source value. Any place in the code that I can look at on how to split a VTSDNode?
> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: Thursday, December 10, 2009 1:25 PM
> To: Villmow, Micah
> Cc: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
> On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
> > Eli,
> > I have a simple SplitVecRes function that implements what you
> mentioned, splitting the LHS just as in BinaryOp, but passing through
> the RHS. The problem is that the second operand is MVT::Other, but when
> casted to an VTSDNode reveals that it is a vector length of the same
> size as the LHS SDValue. This causes a split on the LHS side to work
> correctly, but then it fails instruction selection because of Other. I
> have not been able to figure out how to split the MVT::Other node yet,
> any idea how to do this?
> You should be able to split the contained type with GetSplitDestVTs,
> then recreate the node using SelectionDAG::getValueType(), I think.
> That said, it could possibly be considered a bug in DAGCombine that
> the second operand is a vector type; someone want to comment on that?
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