[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported

[Eli Friedman]

On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Eli,
>  I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS SDValue. This causes a split on the LHS side to work correctly, but then it fails instruction selection because of Other. I have not been able to figure out how to split the MVT::Other node yet, any idea how to do this?

You should be able to split the contained type with GetSplitDestVTs,
then recreate the node using SelectionDAG::getValueType(), I think.

That said, it could possibly be considered a bug in DAGCombine that
the second operand is a vector type; someone want to comment on that?

-Eli