[LLVMdev] Instructions having variable names as operands
sabre at nondot.org
Thu Dec 14 22:46:27 PST 2006
On Thu, 14 Dec 2006, Seung Jae Lee wrote:
> I am Seung Jae Lee making a LLVM backend for a new architecture XCC. I
> found that the instructions use variable names which actually used in
> the source coding for operands unlike most architectures which use
> usually register names or addresses as operands. LLVM backend examples
> such as ARM, SPARC seem to use register names or addresses for operands.
> How can I implement this on my backend? Would you mind telling me about
> this? Thank you very much.
LLVM virtual register names are eliminated during code generation. For
example, something like this:
%X = add int %Y, %Z
might be code generated to:
add EAX, EBX
LLVM names are discarded very early in the code generator. Does this help
answer your question? If not, can you be more specific?
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