[LLVMdev] Instructions having variable names as operands

[Seung Jae Lee]

Hello.
I am Seung Jae Lee making a LLVM backend for a new architecture XCC.
I found that the instructions use variable names which actually used in the source coding for operands unlike most architectures which use usually register names or addresses as operands.
LLVM backend examples such as ARM, SPARC seem to use register names or addresses for operands.
How can I implement this on my backend?
Would you mind telling me about this?
Thank you very much.

Seung Jae Lee

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Graduate Research Assistant
Dept. of Civil & Environmental Engineering
University of Illinois at Urbana-Champaign
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