[LLVMdev] Use of LLVM in a Machine Simulator.

Joseph Altea infovisionorange at yahoo.ie
Sun Apr 16 08:16:50 PDT 2006

I would look at the backend of the gcc (ARM) cross compiler the pass the generates .s files. These run from a table interface and from AST tree of the intermediate langauge that gcc uses. It is not llvm but it is a mapping mechanism that maps to ARM on one side (half your problem) the other half is the map from llvm byte code to the ast tree which you do not need. 
 Probably taking an ARM assembler map and hand mapping single instructions for all the common stuff would get you going then you could implement something more optimimal if you need. In addition you can optimize llvm bytecode then gen asm or object code depending on your model (Jit I think)
 gcc intermiate code is quite simple and you should be able to remap using their ARM as a model into llvm. Perhaps even use the output of the test-suite into a mapper program that takes their instruction cases and then looks them up in a symbol table and then returns th llvm equivalent map so you could possibly automate the process of the transcoding into ARM assembler (JIT)
 Anyways juswt some ideas to add to your investigation. In addition please let me know what you find. I am working on seeing about making llvm go on MacPPC on OpenBSD because of the secure environment.... 
 regards, and good luck, please let me know how its going... Joseph Aleta(IVO)

Ralph Corderoy <ralph at inputplus.co.uk> wrote: 

I'm slowly getting to grips with what makes up LLVM.  I intend to use it
in a machine simulator, e.g. processor, clock, RAM, UART, and other
devices, where the processor will be one of several.  It would take a
block of target instructions, e.g. ARM, and produce LLVM to simulate
those on the target machine state, and then JIT them to host
instructions and then execute.

The peripheral simulations would be in C and end up as LLVM too so
optimisations could occur across the ARM->LLVM/peripheral->LLVM

Does this sound a good fit so far?

My main question relates to TableGen and decoding the target
instructions.  I was initially going to use something specific to the
task of decoding, e.g. New Jersey Machine Code Toolkit, but wonder if I
could/should make use of the *.td for the various processors already
known to LLVM with a new TableGen back-end?  (I know there isn't support
for ARM yet in LLVM.)  And perhaps the DAG selector is of use in
matching patterns in ARM instructions to the desired LLVM rather than
just doing one ARM instruction at a time production?  (For ARM,
substitute other ISAs, some of which aren't in LLVM.)

I'm looking for guidance so I avoid a dead-end.



LLVM Developers mailing list
LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu

  Switch an email account to Yahoo! Mail, you could win FIFA World Cup tickets. 
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20060416/2f5c2c14/attachment.html>

More information about the llvm-dev mailing list