[LLVMdev] Use of LLVM in a Machine Simulator.

Chris Lattner sabre at nondot.org
Sun Apr 16 16:39:38 PDT 2006

On Sun, 16 Apr 2006, Ralph Corderoy wrote:
> I'm slowly getting to grips with what makes up LLVM.  I intend to use it
> in a machine simulator, e.g. processor, clock, RAM, UART, and other
> devices, where the processor will be one of several.  It would take a
> block of target instructions, e.g. ARM, and produce LLVM to simulate
> those on the target machine state, and then JIT them to host
> instructions and then execute.


> The peripheral simulations would be in C and end up as LLVM too so
> optimisations could occur across the ARM->LLVM/peripheral->LLVM
> boundary.
> Does this sound a good fit so far?

Sure, that makes sense.

> My main question relates to TableGen and decoding the target
> instructions.  I was initially going to use something specific to the
> task of decoding, e.g. New Jersey Machine Code Toolkit, but wonder if I
> could/should make use of the *.td for the various processors already
> known to LLVM with a new TableGen back-end?  (I know there isn't support
> for ARM yet in LLVM.)  And perhaps the DAG selector is of use in
> matching patterns in ARM instructions to the desired LLVM rather than
> just doing one ARM instruction at a time production?  (For ARM,
> substitute other ISAs, some of which aren't in LLVM.)

This would be an interesting direction to take, but it may not be the 
easiest one.  The easiest direction would be to write a hand coded machine 
instruction parser (or use something like the machine code toolkit) and 
then have a switch statement on the opcode to emit LLVM instructions.

Of interest may be this thesis.  It talks about converting alpha code to 
LLVM (among other things): http://llvm.org/pubs/2004-05-JoshiMSThesis.html



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