[LLVMdev] Use of LLVM in a Machine Simulator.
ralph at inputplus.co.uk
Sun Apr 16 03:12:01 PDT 2006
I'm slowly getting to grips with what makes up LLVM. I intend to use it
in a machine simulator, e.g. processor, clock, RAM, UART, and other
devices, where the processor will be one of several. It would take a
block of target instructions, e.g. ARM, and produce LLVM to simulate
those on the target machine state, and then JIT them to host
instructions and then execute.
The peripheral simulations would be in C and end up as LLVM too so
optimisations could occur across the ARM->LLVM/peripheral->LLVM
Does this sound a good fit so far?
My main question relates to TableGen and decoding the target
instructions. I was initially going to use something specific to the
task of decoding, e.g. New Jersey Machine Code Toolkit, but wonder if I
could/should make use of the *.td for the various processors already
known to LLVM with a new TableGen back-end? (I know there isn't support
for ARM yet in LLVM.) And perhaps the DAG selector is of use in
matching patterns in ARM instructions to the desired LLVM rather than
just doing one ARM instruction at a time production? (For ARM,
substitute other ISAs, some of which aren't in LLVM.)
I'm looking for guidance so I avoid a dead-end.
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