[PATCH] D75857: [AMDGPU] Fix using physical registers in vector instructions

[Sebastian Neubauer via Phabricator via llvm-commits]

Flakebi added a comment.

I’ll add a test case. Yes, this is related to the atomic optimizer and ballot intrinsic. There we get e.g. `%0:vgpr_32 = V_MBCNT_LO_U32_B32_e64 $exec_lo, 0, implicit $exec`.


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D75857/new/

https://reviews.llvm.org/D75857