[PATCH] D68203: Add support for (expressing) vscale.

Wed Jan 8 07:59:48 PST 2020

SjoerdMeijer added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/sve-vscale.ll:20
+; CHECK-NEXT:  ret
+define i32 @rdvl_arg() nounwind {
+  %vscale = call i32 @llvm.vscale(i32 16)
----------------
sdesmalen wrote:
> SjoerdMeijer wrote:
> > I don't think I understand this and test case above (haven't looked at the other yet). Essentially I don't understand why we remove the mul with 16.... which we are optimsing away? Is this correct? Where does this constant 16 comes from and what is the meaning of it? It could be I don't understand the RDVL instruction, or the vscale intrinsic definition. Can you explain this?
> Here RDVL stores the current vector register size in bytes into `x0` (multiplied by the immediate, in this case 1).
> Given that there are `vscale x 16 bytes` in an SVE vector, this instruction folds that `mul 16` away into the instruction, in which it is implicit.
> 
Ah, yes, thanks for clarifying. I got confused about bits, bytes, and sizes of everything, but I got it now and see that this makes sense. I will continue looking at this patch a bit more.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68203/new/

https://reviews.llvm.org/D68203