[PATCH] D63650: [ARM] Add MVE interleaving load/store family.

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:130
+// Register list operands for interleaving load/stores
+def VecList2QAsmOperand : AsmOperandClass {
+  let Name = "VecListTwoMQ";
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Could we add a DiagnostigString to these? Something like "operand must be a list of two consecutive q registers in range [q0, q7]".


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Comment at: llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp:1243
 
+static DecodeStatus Decodet2rGPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder) {
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Is this new reg class needed? rGPR should already reject r13 and r15 for v8.1M.


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Comment at: llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp:1427
+                                            raw_ostream &O) {
+  // MVE vector lists are always written as a list of q-registers,
+  // never d-registers. getSubReg will give us the four d-regs making
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Could we use ARM::qsub_<N> instead of ARM::dsub_<N> to get the Q registers?


Repository:
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  https://reviews.llvm.org/D63650/new/

https://reviews.llvm.org/D63650