[PATCH] D63650: [ARM] Add MVE interleaving load/store family.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This adds the family of loads and stores with names like VLD20.8 and
VST42.32, which load and store parts of multiple q-registers in such a
way that executing both VLD20 and VLD21, or all four of VLD40..VLD43,
will distribute 2 or 4 vectors' worth of memory data across the lanes
of the same number of registers but in a transposed order.

In addition to the Tablegen descriptions of the instructions
themselves, this patch also adds encode and decode support for the
QQPR and QQQQPR register classes (representing the range of loaded or
stored vector registers), and tweaks to the parsing system for lists
of vector registers to make it return the right format in this case
(since, unlike NEON, MVE regards q-registers as primitive, and not
just an alias for two d-registers).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D63650

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
  llvm/test/MC/ARM/mve-interleave.s
  llvm/test/MC/Disassembler/ARM/mve-interleave.txt

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