[PATCH] D63650: [ARM] Add MVE interleaving load/store family.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham marked 4 inline comments as done.
simon_tatham added inline comments.


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Comment at: llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp:1243
 
+static DecodeStatus Decodet2rGPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder) {
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ostannard wrote:
> Is this new reg class needed? rGPR should already reject r13 and r15 for v8.1M.
Apparently you're right – which means that the defn of that register class in `ARMRegisterInfo.td` has already been added in error. I'll remove it again.

An understandable error, though, I think: looking at the decoder method for rGPR, it only rejects SP without the feature HasV8Ops, and it always takes me a moment to remember that that feature name actually refers to v8-A only, not v8-M!


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Comment at: llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp:1427
+                                            raw_ostream &O) {
+  // MVE vector lists are always written as a list of q-registers,
+  // never d-registers. getSubReg will give us the four d-regs making
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ostannard wrote:
> Could we use ARM::qsub_<N> instead of ARM::dsub_<N> to get the Q registers?
Apparently so, it turns out, which simplifies these functions. Also I've taken the opportunity to combine them into a template.


Repository:
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  https://reviews.llvm.org/D63650/new/

https://reviews.llvm.org/D63650