[PATCH] D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

Fix the pattern to generate a load with the misaligned address?  That already happens.  The problem is that we have passes that make changes based on the assumption that the instructions are valid.  We make no effort to gracefully handle obviously invalid code, and if we detect it, it is usually in an assert.  I think that the trap is a compromise where it won't trigger any further problems during compilation and will still fail for the user.

I'd really like to print the message without users specifically requesting it.  The reason being that there is no intuitive connection between a runtime fault and the optimization remark emitter.  The AMDGPU isel lowering already uses the same diagnostic infrastructure (except that they don't define their own kind).  Do you have a strong preference to use the ORE instead?


Repository:
  rL LLVM

https://reviews.llvm.org/D50524