[PATCH] D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Fix the pattern to generate a load with the misaligned address? That already happens. The problem is that we have passes that make changes based on the assumption that the instructions are valid.

I mean, fix the patterns so that you materialize the immediate into a register.  That should be enough unless some later pass tries to fold an immediate followed by a load... in which case that pass is still broken because some cases of immediate+load won't show up until after isel (for example, tail-dup can eliminate a PHI node).


Repository:
  rL LLVM

https://reviews.llvm.org/D50524