[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Scott Linder via Phabricator via llvm-commits]

scott.linder added inline comments.


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Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:152
+}
+
+attributes #1 = { nounwind readnone }
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arsenm wrote:
> Should also have a test where the SGPR needs to be increment and restored (though I thought we already had one)
> 
> Also could use versions for non-kernels
This case is actually not scavenging another SGPR, it is just incrementing/decrementing the scratch offset SGPR. I don't know how to coerce CodeGen to do the spilling when the register scavenger is available (i.e. not in scavengeFrameVirtualRegs).


https://reviews.llvm.org/D49448