[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:152
+}
+
+attributes #1 = { nounwind readnone }
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scott.linder wrote:
> arsenm wrote:
> > Should also have a test where the SGPR needs to be increment and restored (though I thought we already had one)
> > 
> > Also could use versions for non-kernels
> This case is actually not scavenging another SGPR, it is just incrementing/decrementing the scratch offset SGPR. I don't know how to coerce CodeGen to do the spilling when the register scavenger is available (i.e. not in scavengeFrameVirtualRegs).
OK, I assumed this was scavenging because you used a variable for it, as well as there being no check line for the restore. You should check the literal chosen register here because it will be fixed for the function, and need to check the restore.


https://reviews.llvm.org/D49448