[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D49448#1166974, @scott.linder wrote:

> Addressed feedback, and added at least one test to exercise the fix and the condition for putting the offset in an SGPR.
>
> I would like to add more tests for `Offset + Size - EltSize` where `Size != EltSize` but I have had some trouble getting a ValueReg with subregisters to survive until the spill occurs. E.g. if I load and store a `<2 x i32>` it is spilled as two distinct `i32`.


You may have better success making all of these register clobbers in a single asm statement. Also -stress-regalloc will probably help make this simpler.

This is also a candidate for just making it a MIR test, but in this case I would probably prefer if the IR test worked



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Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:89
+  ; 0x40000 / 64 = 4096 (for wave64)
+  ; CHECK: s_add_u32 [[SGPR:s[0-9]+]], s{{[0-9]+}}, 0x40000
+  ; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], [[SGPR]] ; 4-byte Folded Spill
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You can check the literal SGPR used for this


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Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:152
+}
+
+attributes #1 = { nounwind readnone }
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Should also have a test where the SGPR needs to be increment and restored (though I thought we already had one)

Also could use versions for non-kernels


https://reviews.llvm.org/D49448