[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Scott Linder via Phabricator via llvm-commits]

scott.linder updated this revision to Diff 156125.
scott.linder added a comment.
Herald added a subscriber: qcolombet.

Addressed feedback, and added at least one test to exercise the fix and the condition for putting the offset in an SGPR.

I would like to add more tests for `Offset + Size - EltSize` where `Size != EltSize` but I have had some trouble getting a ValueReg with subregisters to survive until the spill occurs. E.g. if I load and store a `<2 x i32>` it is spilled as two distinct `i32`.


https://reviews.llvm.org/D49448

Files:
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  test/CodeGen/AMDGPU/spill-offset-calculation.ll

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