[PATCH] D43367: [X86] Turn selects with constant condition into vector shuffles during DAG combine

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D43367#1010413, @craig.topper wrote:

> For the shuffle mask problem, can I just force undef to 0?


If you mean always select the undef lane from a specific operand, then yes, that's a valid option. So:
select <0, undef, 0, 1> %x, %y 
becomes:
select <0, 0, 0, 1> %x, %y
becomes:
shuffle %x, %y, <4, 5, 6, 3>

We could do better than that though, and this was mentioned in the IR bug. If we know that the select can be eliminated entirely by choosing from one operand or the other, then that's always a win. We get this half-right in IR - which looks like a shortcoming in InstCombiner::SimplifyDemandedVectorElts():

  define <3 x i8> @sel_x_better(<3 x i8> %x, <3 x i8> %y) {
    %s = select <3 x i1><i1 1, i1 undef, i1 1>, <3 x i8> %x, <3 x i8> %y
    ret <3 x i8> %s
  }
  
  define <3 x i8> @sel_y_better(<3 x i8> %x, <3 x i8> %y) {
    %s = select <3 x i1><i1 0, i1 undef, i1 0>, <3 x i8> %x, <3 x i8> %y
    ret <3 x i8> %s
  }



  $ ./opt -instcombine sel.ll -S
  
  define <3 x i8> @sel_x_better(<3 x i8> %x, <3 x i8> %y) {
    ret <3 x i8> %x
  }
  
  define <3 x i8> @sel_y_better(<3 x i8> %x, <3 x i8> %y) {
    %s = select <3 x i1> <i1 false, i1 undef, i1 false>, <3 x i8> %x, <3 x i8> %y
    ret <3 x i8> %s
  }


https://reviews.llvm.org/D43367