[PATCH] D43367: [X86] Turn selects with constant condition into vector shuffles during DAG combine

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I'm not trying to get rid of SHRUNKBLEND. I'm trying to fix the code to do what it thinks it is doing. It currently checks that the condition is only used by other VSELECTS, but it does this after the call to SimplifyDemandedBits. SimplifyDemandedBits has a one use check inside it that forces the demanded mask to all 1s. So if there were other users(selects or not) we didn't simplify anything that requires a SHRUNKBLEND to be created. So I tried to pre-check for the VSELECT usages and pass in the AssumeSingleUse flag to disable the force to 1s. Then I started seeing poor codegen because we weren't able to constant fold the SHRUNKBLEND to a shuffle.

For the shuffle mask problem, can I just force undef to 0? I believe that's what the sign extend from type promotion was doing already. Though in the AVX512 case we're probably doing the wrong thing today because won't type promote and convert to shuffle during lowering the same way I did in this patch.


https://reviews.llvm.org/D43367