[PATCH] D43367: [X86] Turn selects with constant condition into vector shuffles during DAG combine

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 16 13:04:16 PST 2018

spatel added a comment.

In https://reviews.llvm.org/D43367#1010677, @spatel wrote:

> We could do better than that though, and this was mentioned in the IR bug. If we know that the select can be eliminated entirely by choosing from one operand or the other, then that's always a win. We get this half-right in IR - which looks like a shortcoming in InstCombiner::SimplifyDemandedVectorElts():

This looks fine in DAGCombiner via the undef support in:

  // Fold (vselect (build_vector all_ones), N1, N2) -> N1
  if (ISD::isBuildVectorAllOnes(N0.getNode()))
    return N1;
  // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
  if (ISD::isBuildVectorAllZeros(N0.getNode()))
    return N2;

...so we shouldn't regress those cases at least.


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