[PATCH] D28891: add support for Cavium ThunderX ARM64 processors

Javed Absar via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 19 07:18:35 PST 2017

javed.absar added a comment.

Some comments specifically on the scheduler. Overall the sched-model looks  good, although I don't have the detailed latency and micro-architecture information of ThunderX.

A few points you may want to consider :

1. You could remove the lines with 'let ResourceCycles = [1];' as that's by-default. That would help you reduce size of descriptions in a number of places.

2. Same for 'let Latency = 1;'

3. I don't know the micro-arch of ThunderX, but is there a typo for the latency of THXT8XWriteVST3 as it exceeds corresponding resource-cycle for the same sched-class. You may want to just double-check that.

4. ReadAdvance seems to exceed write latency in some cases, and so you may want to double check that - e.g. ReadI (2) verus WriteI (1).

Best Regards



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