[PATCH] D16734: [AArch64] Simplify prolog/epilog callee save/restore. NFC.

Geoff Berry via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 1 09:23:00 PST 2016

gberry marked an inline comment as done.

Comment at: lib/Target/AArch64/AArch64FrameLowering.cpp:682
@@ +681,3 @@
+    const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI,
+    SmallVector<RegPairInfo, 8> &RegPairs) {
george.burgess.iv wrote:
> Can this take a `SmallVectorImpl<RegPairInfo> &` instead?
Thanks, I hadn't learned that trick yet.

Comment at: lib/Target/AArch64/AArch64FrameLowering.cpp:687
@@ -680,3 +686,3 @@
   for (unsigned i = 0; i < Count; i += 2) {
     unsigned idx = Count - i - 2;
george.burgess.iv wrote:
> It seems that you always add `Count/2` elements to `RegPairs`. Is there any harm in reserving this amount of space in `RegPairs` ahead of time?
The number of RegPairs added is going to change in my next patch (and be less predictable up front), so I'm not sure this makes sense.  It will still be possible to reserve an upper bound in the next change (with the possibility of not using all of the reserved space).  Do you still think this is worth doing in light of that?


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