[PATCH] Fix bug in GPR to FPR moves in PPC64LE
hfinkel at anl.gov
Thu Oct 9 11:53:39 PDT 2014
This LGTM, thanks!
Regarding VSX in FastISel, it needs a lot of work in general. Regarding whatever you have already implemented, so long as it can be regression-tested, you're fine to post it for review now.
----- Original Message -----
> From: "Samuel F Antao" <sfantao at us.ibm.com>
> To: llvm-commits at cs.uiuc.edu, wschmidt at linux.vnet.ibm.com, seuer at linux.vnet.ibm.com, "Hal Finkel" <hfinkel at anl.gov>
> Sent: Thursday, October 9, 2014 1:16:32 PM
> Subject: [PATCH] Fix bug in GPR to FPR moves in PPC64LE
> Hi all,
> The current implementation of GPR->FPR register moves uses a stack
> slot. This mechanism writes a double word and reads a word. In
> big-endian the load address must be displaced by 4-bytes in order to
> get the right value. In little endian this is no longer required.
> This patch fixes the issue and adds LE regression tests to
> fast-isel-conversion which currently expose this problem.
> This move can be done using the VSX capabilities that are currently
> deactivated due to some other problems. I understand Bill and Bill
> are fixing some of the VSX issues in FastISel, but this patch seems
> to be orthogonal to that. I can contribute another implementation of
> the moves using these instructions, which I've already implemented,
> once it is okay to activate VSX for little endian.
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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