[PATCH] Fix bug in GPR to FPR moves in PPC64LE

Bill Schmidt wschmidt at linux.vnet.ibm.com
Thu Oct 9 11:57:10 PDT 2014

On Thu, 2014-10-09 at 14:16 -0400, Samuel F Antao wrote:
> Hi all,
> The current implementation of GPR->FPR register moves uses a stack
> slot. This mechanism writes a double word and reads a word. In
> big-endian the load address must be displaced by 4-bytes in order to
> get the right value. In little endian this is no longer required. This
> patch fixes the issue and adds LE regression tests to
> fast-isel-conversion which currently expose this problem.
Thanks, Samuel!  LGTM.

> This move can be done using the VSX capabilities that are currently
> deactivated due to some other problems. I understand Bill and Bill are
> fixing some of the VSX issues in FastISel, but this patch seems to be
> orthogonal to that. I can contribute another implementation of the
> moves using these instructions, which I've already implemented, once
> it is okay to activate VSX for little endian.
Well, we will need to add a feature for ISA 2.07 (thanks for that fix,
btw) vector support before the direct move instructions can be used.
Currently FeatureVSX implies only ISA 2.06 support, which is all that's
been (partially) implemented at this point.  Probably something like
FeatureP8Vector to denote the changes to both VMX and VSX instructions
for 2.07.

> Thanks!
> Samuel

More information about the llvm-commits mailing list