[llvm-bugs] [Bug 44600] New: [AArch64][ARM] experimental.vector.reduce without FMF asserts

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=44600

            Bug ID: 44600
           Summary: [AArch64][ARM] experimental.vector.reduce without FMF
                    asserts
           Product: libraries
           Version: 10.0
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: nikita.ppv at gmail.com
                CC: arnaud.degrandmaison at arm.com,
                    llvm-bugs at lists.llvm.org, peter.smith at linaro.org,
                    Ties.Stuij at arm.com

define float @test_fadd_ordered(<3 x float> %v) {
  %res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float
0.0, <3 x float> %v)
  ret float %res
}

define float @test_fmax_unordered_nan(<4 x float> %v) {
  %res = call reassoc float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x
float> %v)
  ret float %res
}

declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float
%start_value, <3 x float> %a)
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)

The first case asserts on both AArch64 and ARM because there is no support for
legalizing VECREDUCE_STRICT. The second one asserts on AArch64 because it
requires fmax reductions to be nnan.

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