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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AArch64][ARM] experimental.vector.reduce without FMF asserts"
href="https://bugs.llvm.org/show_bug.cgi?id=44600">44600</a>
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<th>Summary</th>
<td>[AArch64][ARM] experimental.vector.reduce without FMF asserts
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>10.0
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: AArch64
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>nikita.ppv@gmail.com
</td>
</tr>
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<th>CC</th>
<td>arnaud.degrandmaison@arm.com, llvm-bugs@lists.llvm.org, peter.smith@linaro.org, Ties.Stuij@arm.com
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<p>
<div>
<pre>define float @test_fadd_ordered(<3 x float> %v) {
%res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float
0.0, <3 x float> %v)
ret float %res
}
define float @test_fmax_unordered_nan(<4 x float> %v) {
%res = call reassoc float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x
float> %v)
ret float %res
}
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float
%start_value, <3 x float> %a)
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)
The first case asserts on both AArch64 and ARM because there is no support for
legalizing VECREDUCE_STRICT. The second one asserts on AArch64 because it
requires fmax reductions to be nnan.</pre>
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