[llvm-bugs] [Bug 36827] New: [X86] SkylakeClient scheduler model doesn't know that client has less vector ALUs than server

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36827

            Bug ID: 36827
           Summary: [X86] SkylakeClient scheduler model doesn't know that
                    client has less vector ALUs than server
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

For example, skylake client only has 2 vector mutltipliers on ports 0 and 1.
But we have this in the scheduler model.

def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
  let Latency = 4;
  let NumMicroOps = 1;
  let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQrr")>;

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