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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] SkylakeClient scheduler model doesn't know that client has less vector ALUs than server"
href="https://bugs.llvm.org/show_bug.cgi?id=36827">36827</a>
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<th>Summary</th>
<td>[X86] SkylakeClient scheduler model doesn't know that client has less vector ALUs than server
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>For example, skylake client only has 2 vector mutltipliers on ports 0 and 1.
But we have this in the scheduler model.
def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQrr")>;</pre>
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