[llvm-bugs] [Bug 37989] New: [DAGCombine] Call TargetLowering::SimplifyDemandedVectorElts from supported ops
llvm-bugs at lists.llvm.org
Fri Jun 29 09:12:16 PDT 2018
Bug ID: 37989
Summary: [DAGCombine] Call
OS: Windows NT
Component: Common Code Generator Code
Assignee: unassignedbugs at nondot.org
Reporter: llvm-dev at redking.me.uk
CC: andrea.dibiagio at gmail.com, craig.topper at gmail.com,
efriedma at codeaurora.org, filcab at gmail.com,
lebedev.ri at gmail.com, llvm-bugs at lists.llvm.org,
spatel+llvm at rotateright.com
As mentioned on [Bug #37890], we currently only use SimplifyDemandedVectorElts
in the DAGCombiner DAGCombiner::visitVECTOR_SHUFFLE.
We should add support/tests for calling from DAGCombiner::vist* for all the
supported vector ops:
ISD::INSERT_SUBVECTOR (and add ISD::EXTRACT_SUBVECTOR support)
ISD::INSERT_VECTOR_ELT (and call from DAGCombiner::visitEXTRACT_VECTOR_ELT)
Other possible useful operations to add include the various ISD::*EXTEND ops
and we should support passthrough handling of the same AND/OR/XOR/ADD/SUB/MUL
(+SHL/SRL/SRA?) operations as InstCombiner::SimplifyDemandedVectorElts.
Once those are in place we can start adding any necessary target opcodes
through SimplifyDemandedVectorEltsForTargetNode etc.
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