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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [DAGCombine] Call TargetLowering::SimplifyDemandedVectorElts from supported ops"
href="https://bugs.llvm.org/show_bug.cgi?id=37989">37989</a>
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<th>Summary</th>
<td>[DAGCombine] Call TargetLowering::SimplifyDemandedVectorElts from supported ops
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Common Code Generator Code
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, craig.topper@gmail.com, efriedma@codeaurora.org, filcab@gmail.com, lebedev.ri@gmail.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
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<pre>As mentioned on [<a class="bz_bug_link
bz_status_NEW "
title="NEW - Equivalent vector shuffles emit widely different x86 avx2 code"
href="show_bug.cgi?id=37890">Bug #37890</a>], we currently only use SimplifyDemandedVectorElts
in the DAGCombiner DAGCombiner::visitVECTOR_SHUFFLE.
We should add support/tests for calling from DAGCombiner::vist* for all the
supported vector ops:
ISD::CONCAT_VECTORS
ISD::INSERT_SUBVECTOR (and add ISD::EXTRACT_SUBVECTOR support)
ISD::INSERT_VECTOR_ELT (and call from DAGCombiner::visitEXTRACT_VECTOR_ELT)
ISD::VSELECT
Other possible useful operations to add include the various ISD::*EXTEND ops
and we should support passthrough handling of the same AND/OR/XOR/ADD/SUB/MUL
(+SHL/SRL/SRA?) operations as InstCombiner::SimplifyDemandedVectorElts.
Once those are in place we can start adding any necessary target opcodes
through SimplifyDemandedVectorEltsForTargetNode etc.</pre>
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