r367403 - [RISCV] Support 'f' Inline Assembly Constraint

[Sam Elliott via cfe-commits]

Author: lenary
Date: Wed Jul 31 02:45:55 2019
New Revision: 367403

URL: http://llvm.org/viewvc/llvm-project?rev=367403&view=rev
Log:
[RISCV] Support 'f' Inline Assembly Constraint

Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.

Reviewers: asb, lewis-revill

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65500

Modified:
    cfe/trunk/lib/Basic/Targets/RISCV.cpp
    cfe/trunk/test/CodeGen/riscv-inline-asm.c

Modified: cfe/trunk/lib/Basic/Targets/RISCV.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/RISCV.cpp?rev=367403&r1=367402&r2=367403&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp Wed Jul 31 02:45:55 2019
@@ -71,6 +71,10 @@ bool RISCVTargetInfo::validateAsmConstra
     // A 5-bit unsigned immediate for CSR access instructions.
     Info.setRequiresImmediate(0, 31);
     return true;
+  case 'f':
+    // A floating-point register.
+    Info.setAllowsRegister();
+    return true;
   }
 }
 

Modified: cfe/trunk/test/CodeGen/riscv-inline-asm.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/riscv-inline-asm.c?rev=367403&r1=367402&r2=367403&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/riscv-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/riscv-inline-asm.c Wed Jul 31 02:45:55 2019
@@ -26,3 +26,15 @@ void test_K() {
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+float f;
+double d;
+void test_f() {
+// CHECK-LABEL: define void @test_f()
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
+// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
+  asm volatile ("" :: "f"(f));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d
+// CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
+  asm volatile ("" :: "f"(d));
+}