[Openmp-commits] [PATCH] D76780: [OpenMP] Added memory barrier to solve data race
Bryan Chan via Phabricator via Openmp-commits
openmp-commits at lists.llvm.org
Wed Mar 25 14:06:05 PDT 2020
bryanpkc added a comment.
In D76780#1942144 <https://reviews.llvm.org/D76780#1942144>, @bryanpkc wrote:
> Why doesn't the `KMP_MB` after the store to `th_next_waiting` guarantee that the unblocked thread sees that store?
Answering my own question, the ARM architecture reference manual states that the `DMB` instruction ensures that all affected memory accesses by the PE executing the `DMB` that appear in program order before the `DMB` and those which originate from a different PE, ...which have been Observed-by the PE before the `DMB` is executed, are Observed-by each PE, ...before any affected memory accesses that appear in program order after the `DMB` are Observed-by **that PE**.
I think this means, in this case, that the store of `FALSE` to `th_spin_here` is observed in the correct order only by the releasing thread that issued the `DMB`. Other threads (e.g. the spinning thread) could still see the updates to `th_spin_here` and `th_next_waiting` out of order, unless they also issue `DMB`, which is the fix in this patch.
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