[Mlir-commits] [mlir] [mlir][vector] Account for vector.mask in transfer RAW/WAW checks (PR #228328)

[llvmlistbot at llvm.org]

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@@ -249,6 +253,10 @@ bool mlir::vector::checkSameValueRAW(vector::TransferWriteOp defWrite,
 
 bool mlir::vector::checkSameValueWAW(vector::TransferWriteOp write,
                                      vector::TransferWriteOp priorWrite) {
+  // A write under an enclosing vector.mask does not overwrite all lanes of
+  // the prior write.
+  if (write.isMasked())
----------------
Vaisman wrote:

The first argument is the later write.
Only that write must cover every lane; a region-masked `priorWrite` is still dead when a full unmasked write follows it, which is what `@dead_region_masked_store` checks.
Done in 058887f: the comment now says so.

https://github.com/llvm/llvm-project/pull/228328