[Mlir-commits] [mlir] [AMDGPU][MLIR][NFC] moved enc computation to a dedicated method (PR #189339)
Ravil Dorozhinskii
llvmlistbot at llvm.org
Mon Mar 30 02:08:59 PDT 2026
https://github.com/ravil-mobile created https://github.com/llvm/llvm-project/pull/189339
Tried to adapt `GlobalPrefetchOp` for projects like Triton that do not use `memref`s
>From d89c00a1c55c5f14783833c66b74a563273353d3 Mon Sep 17 00:00:00 2001
From: ravil-mobile <ravil.aviva.com at gmail.com>
Date: Mon, 30 Mar 2026 09:02:50 +0000
Subject: [PATCH] [AMDGPU][MLIR][NFC] moved enc computation to a dedicated
method
---
.../include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td | 4 ++++
.../Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp | 17 ++---------------
mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp | 17 +++++++++++++++++
3 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
index 0f01a46e147f5..5028f17bfa419 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
@@ -1978,6 +1978,10 @@ def AMDGPU_GlobalPrefetchOp :
```
}];
+ let extraClassDeclaration = [{
+ static int32_t getLLVMEncoding(amdgpu::TemporalHint hint, amdgpu::Scope scope, bool isSpeculative);
+ }];
+
let assemblyFormat = [{
$src `[` $indices `]` $temporalHint $cacheScope (`speculative` $speculative^)? attr-dict `:` qualified(type($src))
}];
diff --git a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
index 96d4e5da3388c..0135859404da1 100644
--- a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+++ b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
@@ -3961,22 +3961,9 @@ struct GlobalPrefetchOpLowering
if (chipset < kGfx1250)
return op->emitOpError("is only supported on gfx1250+");
- const TemporalHint hint = op.getTemporalHint();
const bool isSpeculative = op.getSpeculative();
-
- int32_t immArgValue = static_cast<int32_t>(hint);
-
- // Note that only RT and HT can operate in both speculative and
- // non-speculative modes. The other variants (NT_RT, RT_NT, NT_HT, etc.)
- // operate only in the speculative mode and, therefore, do not require
- // toggling the least significant bit for mode changes
- // Temporal hint is encoded in lower bits - i.e. [2:0]
- if (llvm::is_contained({TemporalHint::RT, TemporalHint::HT}, hint))
- immArgValue = isSpeculative ? immArgValue : immArgValue | 1;
-
- // Prefetch scope level is encoded in upper bits - i.e., [4:3]
- immArgValue = static_cast<int32_t>(op.getCacheScope()) << 3 | immArgValue;
-
+ const int32_t immArgValue = GlobalPrefetchOp::getLLVMEncoding(
+ op.getTemporalHint(), op.getCacheScope(), isSpeculative);
IntegerAttr immArgAttr = rewriter.getI32IntegerAttr(immArgValue);
ValueRange indices = adaptor.getIndices();
diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
index e27bd461908cd..9d5850a46e661 100644
--- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
+++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
@@ -1306,6 +1306,23 @@ LogicalResult DsBarrierArriveOp::verify() {
// GlobalPrefetchOp
//===----------------------------------------------------------------------===//
+int32_t GlobalPrefetchOp::getLLVMEncoding(amdgpu::TemporalHint hint,
+ amdgpu::Scope scope,
+ bool isSpeculative) {
+ int32_t immArg = static_cast<int32_t>(hint);
+
+ // Note that only RT and HT can operate in both speculative and
+ // non-speculative modes. The other variants (NT_RT, RT_NT, NT_HT, etc.)
+ // operate only in the speculative mode and, therefore, do not require
+ // toggling the least significant bit for mode changes
+ // Temporal hint is encoded in lower bits - i.e. [2:0]
+ if (llvm::is_contained({TemporalHint::RT, TemporalHint::HT}, hint))
+ immArg = isSpeculative ? immArg : immArg | 1;
+
+ // Prefetch scope level is encoded in upper bits - i.e., [4:3]
+ return static_cast<int32_t>(scope) << 3 | immArg;
+}
+
LogicalResult GlobalPrefetchOp::verify() {
auto src = cast<MemRefType>(getSrc().getType());
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