[Mlir-commits] [mlir] [MLIR][XeGPU] Add more OCP micro scaling format types. (PR #177613)

[Sang Ik Lee]

https://github.com/silee2 created https://github.com/llvm/llvm-project/pull/177613

Add fp4 - e2m1 and fp8 - e8m0 data type.

>From 7d14e66ea20e5ad7c790c68639b92d4d24efe079 Mon Sep 17 00:00:00 2001
From: "Lee, Sang Ik" <sang.ik.lee at intel.com>
Date: Fri, 23 Jan 2026 16:50:36 +0000
Subject: [PATCH] [MLIR][XeGPU] Add more OCP micro scaling format types.

---
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
index d9a785c869c3c..c50bd25df2742 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
@@ -15,7 +15,8 @@ include "mlir/IR/BuiltinTypes.td"
 
 def XeGPU_IntType : AnyTypeOf<[I1, I<4>, I8, I16, I32, I64, SI1, SI8, SI16,
                                SI32, SI64, UI1, UI8, UI16, UI32, UI64]>;
-def XeGPU_FloatType : AnyTypeOf<[F8E4M3FN, F8E5M2, F16, F32, F64, BF16, TF32]>;
+def XeGPU_FloatType : AnyTypeOf<[F4E2M1FN, F8E4M3FN, F8E5M2, F8E8M0FNU, F16,
+                                 F32, F64, BF16, TF32]>;
 def XeGPU_ScalarType: AnyTypeOf<[XeGPU_IntType, XeGPU_FloatType]>;
 def XeGPU_PointerType : AnyTypeOf<[UI64, UI32, I64, I32]>;
 def XeGPU_BaseAddrType